REASON project: course IMEC

A modern HDL-based design flow for FPGA prototyping of ASICs

1. Name of the event: A modern HDL-based design flow for FPGA prototyping of ASICs
2. Type of the event: Tutorial
3. Number of hours or days: 1 day
4. Planned date: 13 April 2003
5. Frequency: one-time event, but may be repeated depending on demand
6. Venue: Poznan - Poland (associated with the DDECS03 conference)
7. Target audience: university teaching staff, PhD. students, engineers from the industry
8. Prerequisites (expected knowledge and experience of participants) Basic knowledge of digital design (including HDLs)
9. Character of the event: International, open
10. Expected fee: 20 EURO
11. Are travel grants available ? No
12. Language of the event: English
13. Number of participants: minimum 10 expected 15
14. Brief description of the programme of the event:

This tutorial is focused on an overview of a modern design flow for prototyping of ASIC chips. HDL models (in VHDL or/and Verilog) are used as a design entry. Outline of the tutorial:
1. Purpose.
2. A modern ASIC design flow conception based on hardware accelerated simulation.
a. General data flow overview.
b. The hardware simulation technology overview.
3. HDL design (VHDL, Verilog).
a. The design entry tools as a different design hierarchical view conception.
b. Preparing a hierarchical HDL project.
c. Automatic test bench generation as simply way to minimize project time verification.
d. Increasing simulation flexibility using PLI procedures.
e. Functional simulation.
f. Code coverage analyze of design verification efficient.
4. Synthesis process.
5. Post-synthesis simulation.
6. Design implementation and hardware accelerated simulation based on FPGA circuit.
a. The HES 2.0 DVM user interface.
b. Design implementation.
c. Design configuration and setup preparing for the hardware accelerated simulation process.
d. Hardware simulation.
e. Comparison of simulation results.